Graeme Jessiman's Page

I've got 15+years experience of using RTL for ASIC & FPGA design.
For past 12 years I've supported the HDL design and verification tools for Mentor.
This includes VHDL, Verilog, SystemVerilog & PSL.
I also support customers on the OVM (Open Verification Methodology) using SystemVerilog, assertions, functional coverage, Transaction Level modelling and constrained random stimulus generation.
For the past 3 years Mentor has sponsored MSc projects at the iSLI on advanced verification and I have been the industrial tutor, teaching & helping the students to learn AVM/OVM.
I support customers with Mentor's Clock Domain Crossing (CDC) verification products.
I also have a specific intertest in D0-254 type saftey critical design flows which is a new requirement for the mil-aero customers.