Low Power Design Blog's Blog Posts Tagged 'DRAM' (5)

Three-dimensional architectures such as chip stacks provide both good and bad news for power-oriented design. At the recent 3D Architectures conference near San Francisco, IBM's Subramanian Iyer could see clear benefits in moving to stacks that make use of through-silicon visa to expand capacity.

 

IBM already makes use of embedded DRAM to increase the amount of available memory in the third- and fourth-level caches that its mainframes and supercomputers employ. His question…

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An accident of history has made it possible to cut the power consumption of DRAMs without making any changes to the command protocol. In fact, as described by University of Maryland researchers Elliott Cooper-Balis and Bruce Jacob in the May/June edition of IEEE Micro, their power-saving enhancement relies on a quirk of the DRAM read protocol.



The posted column address strobe (CAS) command, introduced in 2003, provides the DRAM with the column address within the array one cycle after… Continue

Is parallel-mode double datarate memory hitting the buffers in terms of power consumption at the high end? And, if so, is there anything to replace it? That’s the question panelists sought to answer at the Memcon event in Santa Clara, California late last month.…

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Kingston Technology has demonstrated what happens when power consumption begins to spiral out of control. The company has launched heatspreaders for memory modules that are fitted with pipes for water cooling for those people who like to have the fastest possible PC for gaming.…

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In taking a look at benchmarks run on Tom’s Hardware, Steve Leibson on the Denali Memory Blog reckons DDR3 could be more important for embedded applications than for PCs.…

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