Low Power Design Blog's Blog (61)

Former Electronic Engineering editor Ron Neale has tracked the progress of phase-change memory (PCM) for many years. His work on the technology dates back to when it was first proposed as a rad-hard memory for the military. Since then, PCM has promised to become a universal, low-power memory but, some 40 years, on has still failed to achieve it.

The development of a carbon-nanotube form of PCM could signal a way for the technology to deliver on its promise -…

When Panasonic said it would ship its first parts based on a 32nm high-k, metal-gate process by last October, technical analyst firm Dick James of Chipworks was confident the company would hit its deadline and beat many of the other companies planning HKMG.

It took a while but James says Chipworks has now found a Panasonic…

A little over ten years, David Miller of Stanford University argued that optical interconnects for electronic chips would ultimately become necessary:

“Optics is arguably a very interesting and different physical approach to interconnection that can in principle address most, if not all, of the problems encountered in electrical interconnections.”

Miller found problems…

The advantage of system on-chip (SoC) design is that the architects have a lot of control over the power consumption of the equipment because so much of the logic is tied up in one chip. Potentially, the savings can be big because system software can determine which of the functional units are running at any one time. That is as long as they make use of that control.

Writing for EETimes Designline, Satish Sathe of Applied Micro Circuits…

The battle between ARM and Intel in the mobile-device market has reopened the decade-old debate on whether reduced instruction set computer (RISC) design is more efficient than that of a complex instruction set computer (CISC). 

Because ARM is used in mobile phones and devices where Intel’s Atom struggles to gain a foothold, the natural assumption is that RISC is naturally more energy efficient than CISC. But that is not necessarily the case, especially as…

The best battery is a small one, right? Unfortunately the reality is lot more complex than that and a battery powered system might not last as long without a charge as you think if the battery does not match up well with the system it’s powering.

Keith Odland at Silicon Laboratories has written an overview of battery chemistries and their effect on system…

Writing at Chip Design magazine, John Blyler points to recent research by Chip Design Trends that indicates how power consumption – usually too much – has become less of a cause for respins than other problems. 

The graph used doesn’t show how the number of respins has changed but it suggests that common problems in older projects are now much more under control. The big grower for 2010 was the specification…

David Blaauw and colleagues from the University of Michigan – a team that has done a lot of work in near-threshold circuitry and other low-power techniques – have written about their programme to develop radios for tiny, implantable computers at EETimes.

The problem for radio circuitry in systems that need to be powered by a small cell for years on…

The Digital Electronics Blog has posted an “interview question” that asks how much power each implementation of a counter consumes. The design choices are between a standard binary counter, a Gray code counter and a one-hot counter.

In this particular example, the circuit does not have much in the way of leakage current and the power…

The International Symposium on Quality Electronic Design takes place in Santa Clara next week. This year it has a focus on low-power design with a number of tutorials from engineers at companies such as Intel, Qualcomm and CSR.

Muhammad Khellah of Intel will give a tutorial on SRAM and logic circuit techniques for 32nm processes and below. Christopher Chun from Qualcomm will talk about system-level power…

It’s taken a while for USB 3.0 to get off the ground and Apple’s adoption of the Thunderbolt protocol in its latest laptops will not have helped much. But, writing at his blog at Low Power Design, John Donovan points out that USB 3.0 has some significant advantages over its predecessor in terms of power management:

“How can they do that you ask?”

“For starters, by…

Although it doesn’t contain anything specific to low-power design, the recent release of version 1.0 of the Universal Verification Methodology (UVM) will probably make life a little easier when it comes to…

It’s the International Solid State Circuits Conference (ISSCC) this week and Monday featured a panel session on our favourite topic, power reduction, as EETimes’ Dylan McGrath reports. And each of the six panelists picked a different answer as to how best to tackle the problem.

Veteran microprocessor designer Dan Dobberpuhl explained: “I…

System-Level Design has been running a short series of round tables with a group of experts from EDA companies in embedded system-level (ESL) design that contain some snippets and thoughts on using high-level approaches to improve efficiency and power consumption.

One of the issues they touch on is the shelf life of intellectual property (IP) and how that relates to runtime…

The SOI Industry Consortium claims to have shown that using fully depleted silicon-on-insulator (FD-SOI) processes can do a lot to reduce power consumption in memories as well as logic circuits.

At an event after the International Electron Device Meeting (IEDM), the consortium put up speakers such as Thomas Skotnicki…

In the latest issue of Chip Design magazine, Shabtay Matalon of Mentor Graphics writes about designing for low power at the system level.

The big problem with working at the system level is that, without a clear idea of implementation, it is hard to get hard numbers for the power consumption of individual blocks and trade off different approaches against each other. Tools are appearing that will at least…

There is no shortage of materials queuing up to take over from silicon. The latest is molybdenum disulphide, following work to improve its properties Swiss EPFL research institute. Despite the material’s poor electron mobility, EPFL has claimed it could be an alternative to graphene for the semiconductors of the future, with some big claims…

The .lib or Liberty format has been used for years to provide circuit simulators with timing information for transistors and other devices. But, writes Karen Bartleson on her blog about standards for Synopsys, the attention within the group that oversees the .lib format has shifted in recent years towards power modelling.

The Liberty Technical Advisory Board (LTAB) has…

To me, it always seems slightly ironic that utility meters need to have ultralow power consumption when they often sit right next to a massive energy source. But, unless they are electricity meters, they will often have to run for years off a battery.

Writing for EETimes DesignLine, Sunil Deep Maheshwari and Prashant Bhargava from Freescale Semiconductor take a…

In a blog for Chip Design, Mentor Graphics solutions architect Barry Pangrle writes about the need to move some functions into hardware to save power. 

He writes: “Processors emulate functionality and there’s generally a significant overhead from an energy standpoint for having a flexible programmable implementation.”

The difference, as Pangrle points out, can be illustrated by the Octeon II…