Abstractions and ESL

System-Level Design has been running a short series of round tables with a group of experts from EDA companies in embedded system-level (ESL) design that contain some snippets and thoughts on using high-level approaches to improve efficiency and power consumption.

One of the issues they touch on is the shelf life of intellectual property (IP) and how that relates to runtime efficiency. Thomas Bollaert, product marketing manager for Mentor Graphics’ high-level synthesis product line, says: “As you shrink the nodes, the IP may still work but it becomes sub-optimal. The need to re-optimise for a new technology node and avoid power issues and integrity issues isn’t easy.”

Brett Cline, vice president of marketing and sales at Forte Design Systems, argues: “Customers are now starting to take a look at the IP they’ve been buying and do it themselves because they can trim off 10% of the area or lower the power to spec or add some unique value—and maybe even do it more efficiently. We’re seeing more people move to their own internal IP model.”

However, Johannes Stahl, director of marketing for system-level solutions at Synopsys, counters: “That only holds for IP that’s specific to their products. Nobody in their right mind should do standard IP today by themselves. It’s not economical.”

In the third part, the experts talk about the TLM 2.0 standard and how the trend is to validating architectures for performance or power ahead of building RTL.

Posted by Chris Edwards

The Low-Power Design Blog is sponsored by Mentor Graphics. The company has focused years of R&D on low-power design techniques and is glad to support a resource that highlights creative methods for reducing the power consumption of electronic systems.