Back to the future as CISC vs RISC argument reopens

The battle between ARM and Intel in the mobile-device market has reopened the decade-old debate on whether reduced instruction set computer (RISC) design is more efficient than that of a complex instruction set computer (CISC). 

Because ARM is used in mobile phones and devices where Intel’s Atom struggles to gain a foothold, the natural assumption is that RISC is naturally more energy efficient than CISC. But that is not necessarily the case, especially as Renesas Technology has pitched in claiming to Electronics Weekly that its CISC architecture underlying the RX processor family uses less power than a comparable RISC-based design.

Renesas is not alone in believing this. Researchers such as David Blaauw of the Unversity of Michigan are actively investigating the use of CISC architectures because of their power properties. Just because some of the most power-hungry processors you can buy today are based on CISC, it does not mean that the architectural concept is broken.

As I wrote last year in New Electronics (26 October, 2010), researchers such as David Balfour, formerly of Stanford University and now at nVidia, have done a lot of work on characterising the power consumption of processors. Computation is extremely efficient: it’s memory accesses that chew up the watts. And this is where CISC can begin to win.

The reason why RISC became popular is because, during the 1980s, compiler technology was comparatively primitive. They simply could not cope with the complex addressing modes and instruction options that CISC architectures could provide. The result was that CISCs had a lot of extra baggage for no real gain. 

Second, instruction throughput was the primary concern. CISC architectures such as the x86 had evolved a Byzantine instruction set that was not very easy to pipeline – you had to almost completely decode each instruction to work out where the next one was. The instruction encoding was very storage efficient but this became less important over time as memory prices plummeted (although ARM had to compromise on this when it sold Nokia on the promise of its processor architecture). You always knew where the next RISC instruction was because each had a fixed length: and that remained the case in ARM’s Thumb.

However, RISC tends to demand a lot of memory moves. In performance terms, these can be hidden by pipelining, caching and large register files. But you can’t hide the power consumption of those memory moves so easily. That’s why Blaauw’s group is using more complex addressing modes to allow fetches and writes to be computed in one go instead of using several instructions to shovel intermediate data around registers. The intention is not to rebuild the massive multicycle instructions of the 32bit x86 architecture. Then again, even many of those are simply emulated today using microcode and software writers are advised to stick to a reduced, core set of instructions. As a result, the x86 wound up as a slightly RISCified CISC machine.

Which is better? In practice, a mixture of both. The real question is how each architecture saves on memory accesses and packs as much practical work into computation as possible.

Posted by Chris Edwards

The Low-Power Design Blog is sponsored by Mentor Graphics. The company has focused years of R&D on low-power design techniques and is glad to support a resource that highlights creative methods for reducing the power consumption of electronic systems.