CMOS Variability, Its Impact on Reliability, and the Need for DfX

With the Second International Conference on CMOS Variability starting on 12th May, my thoughts are turning to the impact of scaling on device reliability.

A memorable presentation I saw on this topic was given in October 2008 by Prof Asen Asenov at NMI’s Design for Manufacture Technical Network in Cambridge. The visual impact of one of the slides has stayed with me as it clearly showed the increasing significance of individual atoms (whether intentional dopants or random defects) as the size of a transistor gate becomes smaller.

http://www.nanocmos.ac.uk is a website which describes itself as “Meeting the design challenges of nano-CMOS Electronics”. It contains many references to CMOS Variability and the work of Prof Asenov’s device modelling group at the University of Glasgow, and there are some useful presentations available for download.
An interesting consequence of scaling is that we are approaching a scenario where we will no longer expect the whole of a chip to be functional, and where the functional areas will actually vary from die to die. This calls for a programmable architecture which allows us to select the “good” areas , and potentially to utilise programmability throughout - allowing the design itself to be fine-tuned after manufacture.

Another consequence of scaling was raised by Dr Kerstin Eder at NMI’s DVClub at the January 2009 meeting in Bristol. Her overview of current research in the field of Design Verification and Automation made reference to the work of Marta Kwiatkowska at Trinity College Oxford on Modelling and Quantitative Verification of Probabilistic Systems. The research shows that as a set of standard circuit elements is progressively shrunk, failures occur following a probabilistic pattern. The mathematical modelling of the failures is described in a paper entitled “PRISM: Probabilistic Model Checking for Performance and Reliability Analysis” which is available at http://qav.comlab.ox.ac.uk/bibitem.php?key=KNP09a

My personal view is that the four major threats to the future of scaling are (in no particular order): Signal Integrity, Reliability, Robustness of Design, and Cost Effectiveness. I’ll explore some of these other areas another time, but for the time being I’ll concentrate on Variability and its impact in Reliability.

It is increasingly apparent that the definition and application of DfX rules (Design for Reliability, Design for Analysis, Design for Test etc.) will become more significant as we move to smaller process dimensions. In an ideal world the design tool companies would be building front-end DfX packages into their software. However the economic reality of the situation is that no-one is going to spend money developing a product that the customer hasn’t asked for yet. Another economic reality is that while most people think that DfX is a good idea, but no one wants to spend an money on it !

Make no mistake – Variability is Real. Exactly how hard or how soon it will hit is not clear, and we have 3 options:
1) Bury heads in the sand.
2) Bemoan the fact we have no resource.
3) Put some contingencies in place.

I would advise option 3. The bare minimum is to define and implement DfX guidelines, but ultimately we will need DfX Tools. In my view this will be the next economic reality.
The Second International Conference “Living With CMOS Variability” is at Savoy Place, London on 12-13 May. http://www.nmi.org.uk/events/event-details/nmi-iccv-2009