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The Digital Electronics Blog has posted an “interview question” that asks how much power each implementation of a counter consumes. The design choices are between a standard binary counter, a Gray code counter and a one-hot counter.

In this particular example, the circuit does not have much in the way of leakage current and the power from clocking can be neglected (which would probably do a lot to cover up any real-world differences in implementation). It also assumes that the combinational circuit’s capacitive load in each case, on a per-signal basis, is twice that of the flip-flop.

The blog doesn’t give an answer but illustrates some of the tradeoffs that turn up in low-power design. However, in today’s processes, the question may really be: how long does that counter need to be powered for? Leakage does tend to creep up on you.

 

Posted by Chris Edwards

The Low-Power Design Blog is sponsored by Mentor Graphics. The company has focused years of R&D on low-power design techniques and is glad to support a resource that highlights creative methods for reducing the power consumption of electronic systems.

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