IEEE1149.X JTAG Boundary Scan - Who knows what it is used for?

Hello Everyone,
I was in a discussion with a group of EDA tool vendors and DfT engineers last week regarding the uses of JTAG in the design and test communities and I was shocked to hear from both sides that there still seems to be some confusion as to what we can use the IEEE1149.1X standard for in our IC, PCB and System designs. Some think it is only an access port for testing interconnects on PCBs, others look at it as only capable of In-System Configuration programming while others only recognise on-chip debug. It really can do all of these..............

Let's consider each of the designs in turn and look at the value add that can be achieved:

IC design: Value of Boundary Scan at Chip Level
1. Reduced Pin Count Test (RPCT)
2. DC parametric measurements, including pin leakage
3. General-purpose BIST controller (MBIST, LBIST)
4. Scan-thru-Tap and other register access
5. PLL controller
6. IDDQ control
7. Burn-in controller
8. Fault injection via the BSR
9. IEEE 1500 ECT
10. Emulation (IEEE 5001)

PCB Design: Value of Boundary Scan at PCB Level
1. Short test programming time
2. PCB manufacturing defects: Infrastructure, Interconnect, non-B’Scan components tested
3. Can use low-cost PC-based testers: no fixtures – edge-connector is enough
4. Effective defect detection/location (via Scan-thru-TAP or BIST): aids board debug
5. Only solution for MCMs/SiPs and limited-access SMT/ML boards
6. Enables In-System Configuration: CPLD, Flash, FPGA, PROM
7. System/field diagnosis: 1149.1 is the “internet of test”.
8. On-Chip Debug solutions

System Design: Value of Boundary Scan at System Level
1. Prototype system debug prior to commitment to system volume production
2. System commissioning prior to shipment to the customer
3. Field service and Repair Depot
4. Board-to-board interconnect testing
5. Configuration learning
6. Functional testing
7. Operating testing in background mode
8. Perform tests automatically on power up

To name but a few....

All of the above can be carried out across the 4, optionally 5, TAP interface pins, and with the latest 1149.7 standard you can now go down to just 2 pins. New standards based on the original IEEE1149.1 JTAG concept are already being thought about by working parties dedicated to the improvement of test and reliability through the use of boundary scan - IJTAG, cJTAG, SJTAG to name but 3. Keep watching, JTAG is not dead yet......

While you are here, please take time to take the following Design for Test and Reliability survey. It will only take 3-5 minutes to complete: http://tinyurl.com/p9n4qh

Comments from the community always welcome............