Plan ahead for low-power design

It won’t be long before the next DVCon rolls around in the US and the problems of verifying low-power designs are becoming more apparent. The one piece of advice that engineers working in the field stress is that it’s important to plan ahead when doing anything to reduce the overall power consumption of chip designs.

One of the key papers at DVCon from 2009 – it won best paper for that year– but one that is still relevant is Low Power Verification Methodology Using UPF by engineers from Texas Instruments and Mentor Graphics.

The paper describes a “holistic approach to power-aware verification”, using design information captured as Unified Power Format (UPF) statements to help drive the verification process. 

To make effective use of UPF, the chip needs to be partitioned into power and retention domains with well-defined isolation so that powered-off domains wind up with unexpected logic values when they wake up again. It means having a well-defined power architecture in place before setting out to add power-down modes and details such as state-retention registers.

The paper provides a brief overview of UPF, a checklist for verification and show the kinds of bugs the designers caught using this flow. So it works as a good introduction for people moving into power-aware verification.

Posted by Chris Edwards

The Low-Power Design Blog is sponsored by Mentor Graphics. The company has focused years of R&D on low-power design techniques and is glad to support a resource that highlights creative methods for reducing the power consumption of electronic systems.