Power-related respins plummet (or do they?)

Writing at Chip Design magazine, John Blyler points to recent research by Chip Design Trends that indicates how power consumption – usually too much – has become less of a cause for respins than other problems. 

The graph used doesn’t show how the number of respins has changed but it suggests that common problems in older projects are now much more under control. The big grower for 2010 was the specification change – which indicates either that a lot of companies have suddenly suffered a late-stage course correction or that the number of respins has shrunk, exposing those organisations that haven’t quite got the specification thing nailed.

Blyler offers another explanation,  which is plausible: “[It] might be that power issues are appearing in another guise, which might explain the continued prominence of specification changes, signal integrity and analog performance as causes for respins. Changing specification for power budgets – especially during the later stages of a design – can easily lead to design errors. Signal integrity issues can arise from more clocks running at faster speeds and consuming more power.”

Grant Martin’s blog may offer another way of looking at this. So far, the EDA industry has focused largely on virtual prototyping as a way of checking complex, software-intensive. These do a great job of testing whether the design works, but do not necessarily give a good indication of target power consumption. Martin calls for more attention to be given to higher-level design to help design these complex systems – understanding the tradeoffs earlier would help nail down a specification properly before implementation. And a specification with a realistic idea of the power budget.

Posted by Chris Edwards

The Low-Power Design Blog is sponsored by Mentor Graphics. The company has focused years of R&D on low-power design techniques and is glad to support a resource that highlights creative methods for reducing the power consumption of electronic systems.