Resize transistors for better leakage

At the recent ARM Techcon, as reported by Low-Power Design magazine, ARM platform manager Wolfgang Helfricht recommended designers use all manner of techniques to save power. But he singled a couple out as particularly useful.

One is to not go for the minimum transistor dimensions but to relax the channel length a little to cut down leakage, a technique that has been used by a number of people in the cell-library business. This slows the transistor down but if it’s not on a critical path it can improve its leakage performance.

“We can achieve large leakage performance improvements of up to 20 percent with very fine resolution,” Helfricht said, adding that the use of longer-channel transistors in cell coupled with multiple thresholds has led to a dramatic increase in cell count. “At 180nm, you could expect to see 1800 cells in a typical SoC design. At 28nm, that number goes up to 12,000 cells.”

The other key thing to watch is memory. As the memory arrays get bigger, the more they dominate the overall equation. Leakage will dominate in large memories. This encourages designers to drop the supply voltage, which makes the memories more sensitive to variability problems. Techniques such as adding write-assist transistors can help reduce the problems caused by shrinking static noise margin.

Posted by Chris Edwards

The Low-Power Design Blog is sponsored by Mentor Graphics. The company has focused years of R&D on low-power design techniques and is glad to support a resource that highlights creative methods for reducing the power consumption of electronic systems.